Resources
Application Notes
Validating STIL Files Before Sending to Test Team
STIL files that are unvalidated could contain hidden issues downstream and only be discovered late by the test team on the physical tester. Not only the time span can be lengthy and causing schedule slippage, but also the problems are more expensive to fix; let alone having a process that is not efficient. TSSI’s high performance software tools have unique capabilities to automate this pre-silicon validation process [READ MORE>>>]
Re-simulating ATE Pattern with Conditional Delayed Start
Often time a test pattern exercises one function of the device-under-test (DUT). If the pattern is re-used at different logic cone within a design, some device initialization needs to take place before the pattern can be applied. [READ MORE>>>]
Optimizing ATE Resources for ATPG Patterns
ATPG patterns today often feature clock signals declared as extensions to default timing in STIL files. Hence, these clock signals use transitional ATE formats NRZ and RZ/R1. This applications note describes one methodology to achieve that goal in a TSSI tool. [Download PDF >>>]
Optimizing Timing Across Multiple for ATPG Files from DFT
DFT teams often deliver many ATPG files in the standard file format such as WGL or STIL for testing the same device. Not only it's beneficial to have an automated process to convert all of these EDA files, but also crucial to produce a single master time set for the target ATE to achieve the best test time of the device.
This applications note describes the NI STS as the target ATE. To target a different ATE, simply drop in the corresponding TesterBridge. [Download PDF >>>]
Free Downloads
The WGL standard specification
WGL stands for Waveform Generation Language created by TSSI in the 1980s. It's the de-facto standard language for design to interface with test, especially in the design-for-test ATPG tools environment. Together with IEEE Std 1450-1999 (STIL) and its extensions, WGL and STIL are currently the most popular languages for ATPG tools to send cycle-based test patterns to test teams. The most recent revision to the WGL spec is in 2017. [Download Spec Here >>>]
Archived Releases
TD-ScanPro 2019.1 Build r4439 Release June 2, 2019 [QuickStart Guide]
TD-ScanPro 2018.0 Build r4081 Release Sep 28, 2018 [QuickStart Guide]
Solstice-TDS 2019.3 Build r4552 Release Aug 12, 2019 [QuickStart Guide]
Frequently Asked Questions
New Customers
Why should I use TSSI vector translation tool?
1. Broadest EDA and ATE Suport. Solstice-TDS supports the most EDA formats and all ATE formats on the market: new and old.
I've used TSSI's vector translation tool "TDS" for many years. Where is it now?
TDS has been renamed Solstice-TDS when TSSI introduced WaveMakerPLUS, the next-generation graphical user interface that allows users seeing their data before, during, and after translation.
What's the diference betwee Solstice-PV and TSSI VirtualTest (TVT)?
Solstice-PV converts ATE patterns to a test bench for re-simulation.
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Multi-site -
Match Loops -
Multiple Time Domain -
DC-level setup -
Pattern microcodes such as: GENV, RPTV, TRIGGER, DSP serial send/receive, etc.
How can I tell if my converted patterns are correct?
The fastest step is to compare the waveforms representation of your final patterns with your pre-converted waveforms (e.g., VCD).
What is TD-ScanPro?
TD-ScanPro is the vector translation tool of choice by NI customers to convert EDA formats (WGL, STIL, VCD, and EVCD) to the NI STS digital pattern format.
What's the difference between TD-SCAN and TD-ScanPro?
TD-SCAN converts WGL and STIL to NI's 654x/5x/6x instruments using HWS format.
Existing Customers
How can I remove signals from an SEF without clicking through the waveform editor?
Just add a Derive Conditioner to your flow. This conditioner reads a text file where you specify the signals to be removed and operate accordingly to the source SEF.
Heard about the Signal Edit Conditioner for WDBs. What can it do?
The Signal Edit Conditioner can add, delete, rename signals. It can also promote uni-directional signals (input & output only) to bi-directional.
I've got too many extraneous signals in my STIL file from design (powers, gnds, etc). What's the easiest way to remove them?
After in-converting the STIL file into TSSI's SDB (STIL waveform database), use the Signal Edit Conditioner's MATCHPINFILE mode to specify exactly which pins to use in your test patterns.
I have hundreds of STIL files to be converted. What's the easiest way?
1. Our GUI (WaveMaker+) has an object called Orbitx which can loop through a Scenario as many times as there are STIL files in a directory. Just tell Orbitx where the files are, and what suffixes (e.g., *.stil or .stil.gz).