Validating STIL Files Before Sending to Test Team
STIL files that are unvalidated could contain hidden issues downstream and only be discovered late by the test team on the physical tester. Not only the time span can be lengthy and causing schedule slippage, but also the problems are more expensive to fix; let alone having a process that is not efficient. TSSI’s high performance software tools have unique capabilities to automate this pre-silicon validation process [READ MORE>>>]
Re-simulating ATE Pattern with Conditional Delayed Start
Often time a test pattern exercises one function of the device-under-test (DUT). If the pattern is re-used at different logic cone within a design, some device initialization needs to take place before the pattern can be applied. [READ MORE>>>]
Optimizing ATE Resources for ATPG Patterns
ATPG patterns today often feature clock signals declared as extensions to default timing in STIL files. Hence, these clock signals use transitional ATE formats NRZ and RZ/R1. This applications note describes one methodology to achieve that goal in a TSSI tool. [Download PDF >>>]
Optimizing Timing Across Multiple ATPG Files from DFT
DFT teams often deliver many ATPG files in the standard file format such as WGL or STIL for testing the same device. Not only it's beneficial to have an automated process to convert all of these EDA files, but also crucial to produce a single master time set for the target ATE to achieve the best test time of the device.
This applications note describes the NI STS as the target ATE. To target a different ATE, simply drop in the corresponding TesterBridge. [Download PDF >>>]
The WGL standard specification
WGL stands for Waveform Generation Language created by TSSI in the 1980s. It's the de-facto standard language for design to interface with test, especially in the design-for-test ATPG tools environment. Together with IEEE Std 1450-1999 (STIL) and its extensions, WGL and STIL are currently the most popular languages for ATPG tools to send cycle-based test patterns to test teams. The most recent revision to the WGL spec is in 2017. [Download Spec Here >>>]
QuickStart Test Cases
STIL to Catalyst Scenario [stil-catalyst.tgz]
STIL to V93000 Scenario [stil-v93000.tgz]
STIL to ASCII Scenario [stil-ascii.tgz]
STIL to Chroma 3360 Scenario [stil-chroma3360.tgz]
Frequently Asked Questions
Why should I use TSSI vector translation tool?1. Broadest EDA and ATE Suport. Solstice-TDS supports the most EDA formats and all ATE formats on the market: new and old. 2. Easy to Use. The graphical programming user interface is easy to use for new users, and instantly reminds casual users of their set up and decisions. There are no propriatery syntax to learn, and zero typing errors. 3. Built for Automation. All setups can be saved as batch files. API package enables full customization and automation. 4. Low cost. Although with enterprise strength, the modular architecture allows customers to only pay for what they use. Solstice-TDS can be rented online as low as $540/month. More benefits, see: tessi.com/solstice-tds
I've used TSSI's vector translation tool "TDS" for many years. Where is it now?"TDS has been replaced by Solstice-TDS, the next-generation tools suite that's more powerful and with modern architecture. Solstice-TDS's WaveMakerPLUS is the unique graphical user interface in the vector translation tools space that allows users seeing their data before, during, and after translation. We don't recommend "blind" translations and then debug the test pattern on the expensive tester afterward. Solstice-TDS also has advanced techniques for validating patterns before silicon arrives. See the description of the Solstice-PV module on the Solstice-TDS product page.
What's the diference betwee Solstice-PV and TSSI VirtualTest (TVT)?Solstice-PV applies EDA- and ATE-neutral cyclized patterns to a Verilog test bench for re-simulation. TVT, on the other hand, models the tester. ATE patterns can be compiled on TVT, much like the operation on the physical ATE, and execute with ATE specific functionalities intact: Multi-site Match Loops Multiple Time Domain DC-level setup Pattern microcodes such as: GENV, RPTV, TRIGGER, DSP serial send/receive, etc. More details at: tessi.com/tvt
How can I tell if my converted patterns are correct?The fastest step is to compare the waveforms representation of your final patterns with your pre-converted waveforms (e.g., VCD). Solstice-TDS has the waveform comparison capabilities where discrepancies are highlighted on an overlay view as red bars. The differences can be searched and reported. Solstice-TDS also has 3 capabilities for pre-silicon pattern validations: Output Verilog testbench for re-simulation (send it back to design team), output VCD/EVCD and send it back to the design team, or use Solstice-PV module to drive the EDA simulator with the cyclized patterns (design and test share the same tool environment). TSSI also has a product called TSSI VirtualTest (TVT). TVT models the tester sequencer, parallel and scan pattern memories, and pin electronics so that the test program can be compiled and simulated as-is without re-converting back to test bench. Details at tessi.com/tvt
What is TD-ScanPro?TD-ScanPro is the vector translation tool of choice by NI customers to convert EDA formats (WGL, STIL, VCD, and EVCD) to the NI STS digital pattern format. TD-ScanPro is a result of the collaboration between TSSI and NI (formerly National Instruments). More details at tessi.com/td-scanpro
What's the difference between TD-SCAN and TD-ScanPro?TD-SCAN converts WGL and STIL to NI's 654x/5x/6x instruments using HWS format. TD-ScanPro converts WGL, STIL, VCD, EVCD to NI STS 657x using digital pattern format and 654x/5x/6x using HWS format. TD-ScanPro is the next-generation software package for NI customers. TD-ScanPro replaces TD-SCAN since 2016 when TD-SCAN was subsequently discontinued. All TD-SCAN customers are encouraged to upgrade to TD-ScanPro with the cost of TD-SCAN fully credited toward TD-ScanPro. For more information, contact: firstname.lastname@example.org
How can I remove signals from an SEF without clicking through the waveform editor?Just add a Derive Conditioner to your flow. This conditioner reads a text file where you specify the signals to be removed and operate accordingly to the source SEF. Documentation of the Derive Conditioner is accessible via Solstice-TDS "Help->Solstice User Manual..."
Heard about the Signal Edit Conditioner for WDBs. What can it do?The Signal Edit Conditioner can add, delete, rename signals. It can also promote uni-directional signals (input & output only) to bi-directional. The applications where the conditioner could be useful include: - Make signal names legal on the tester. Often ATPG tools generate signal names that are illegal on a tester. - Prepare signals to be mergable among IP cores Documentation on Signal Edit Conditioner can be found in Solstice-TDS "Help->Solstice User Manual..."
I've got too many extraneous signals in my STIL file from design (powers, gnds, etc). What's the easiest way to remove them?"After in-converting the STIL file into TSSI's SDB (STIL waveform database), use the Signal Edit Conditioner's MATCHPINFILE mode to specify exactly which pins to use in your test patterns. Documentation accessible via Help->"Solstice User Manual...", or contact: email@example.com.
I have hundreds of STIL files to be converted. What's the easiest way?1. Our GUI (WaveMaker+) has an object called Orbitx which can loop through a Scenario as many times as there are STIL files in a directory. Just tell Orbitx where the files are, and what suffixes (e.g., *.stil or .stil.gz). Documentation on Orbitx can be found via Help->"WaveMaker+ User Manual..." 2. For users preferring command line interface, your Scenario can be saved as an ASCII batch file. Once saved, use your favorite script to loop through all your STIL files and auto-replace the file name in the batch file and run it. Contact: firstname.lastname@example.org