Re-simulating ATE Pattern with Conditional Delayed Start
Often time a test pattern exercises one function of the device-under-test (DUT). If the pattern is re-used at different logic cone within a design, some device initialization needs to take place before the pattern can be applied.
The requirements for re-simulating an ATE pattern accurately and generating useful validation reports are:
1. The start of the pattern must wait until a certain condition (or a combined logic) has been met
2. The reporting of the tester cycle in the pattern must be offset by the actual start of the pattern
This application note describes how Solstice-PV is used to meet the requirements.
1. Delay Start Condition
Consider a DUT with a signal called delayStart, which transitions from 0 to 1 at 10ns. At the 0 to 1 transition, you would like to start the application of the ATE pattern sourced from a TSSI waveforms database (WDB).
Consider the original WDB with stimulus and response starting at 0ns:
Here is the trigger signal:
Here is the desired simulation waveforms:
Here is a step-by-step instructions using the Solstice-PV's VerilogOut Tool:
1. Insert into the Scenario canvas the operation Out->Verilog, and set it up to generate relative timing:
2. Generate a testbench (cmd.v) and edit to replace INITIAL with a customized trigger statement:
3. Cycle Count Display
Using TSSI's SignalEdit Tool to add a signal that will pulse high at the start of every cycle. The testbench will then count the edges and display the count when a pattern mismatch happens:
4. Add a cycleCounter to the testbench file:
5. Update the message displays to include the cycleCount:
The actual test case can be downloaded here: [delayVoutStart.tgz]
Author: David Leslie (May 26, 2020)
Contact TSSI: email@example.com