Portland, Ore., June 21, 2019 - Test Systems Strategies, Inc., ("TSSI") today released its latest installment of the enterprise strength design-to-test pattern conversion and validation tool suite, Solstice-TDS 2019.2.
"As design verification teams around the globe taking on the task of generating and verifying test vectors before silicon to shorten test development schedule, more design-aware capabilities are required in design-to-test vector translation tools such as TSSI's Solstice-TDS." Said Hau Lam, President and CEO at TSSI."
Solstice-TDS 2019.2 is packed with capabilities to address this trend, according to Lam. Several key features are:
- Simulation Rules Checker (or "SRC") assists design verification to detect incorrect protocols, timing specification violation, and other design rules violations in their vectors that would be more costly if caught in later process downstream
- Automatic waveform analysis to examine timings across simulation runs. This feature is designed to be part of regression tests to detect unintended variation by comparing new waveforms to a known-good-waveform.
- Conditional pattern replacement capability helps integrate IP core patterns to construct a full-chip test pattern
- Signal editing tool programmatically integrates STIL files generated by DFT tool at different times for different parts of the device
- Built-in "data experience" enables TSSI's Verilog reader to achieve 100x faster runtime performance and able to automatically generate ATE timing so that design verification teams can deliver verified ATE patterns to their test team.
"As the current explosion of IC content in almost everything demands faster time-to-market and cheaper overall cost," Lam continued, "one obvious area to focus on is to streamline the design-to-test process. Any unncessary iteration to fix undetected bugs is a waste of time, and an increase of overall cost."
Solstice-TDS 2019.2 is available for download now at tessi.com/solstice-tds. Customers on active maintenance can send in request for free upgrade.