Solstice TimeTable™

A Two-Minute Video Story  

Vector Translation with Ease  

While translating ATPG patterns (WGL and STIL formats) is a push-button operation using Solstice-TDS, converting Verilog simulation output (VCD and EVCD) to a tester format involves a process called cyclization.  This process creates cycle-based timing from the event-based VCD/EVCD file. 

With Solstice TimeTable, signals, directions, test period, per-pin timing, and ATE format are all automatically detected and filled in.

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  • Auto-Fill Signals, Directions, and ATE Format.  Just from reading in the VCD/EVCD file, TimeTable can extract and populate the timing table with signal names, their directions, and the detected waveform, hence, ATE format (eg, NRZ, R0, R1, etc).
  • Auto-Detect Cycle Length.  TimeTable can detect the most regulated clock waveform in the source VCD/EVCD file and fills in the cycle length appropriate for cyclization.  If there are more than one found, TimeTable will present the list of periods for the user to choose from.
  • Auto-Detect Per-pin Timing.  TimeTable performs a comprehensive analysis of all events in the VCD/EVCD file and constructs ATE-waveform and timing that conform to the target ATE's rules.  This feature is key in ensuring all intended behaviors in the simulation event are preserved.  Without it, tests could fail good parts, or worse, bad parts are being passed (which is often the case when tools and engineers short cut pattern generation step).
  • Comprehensive viewing and resolving issues of complex timing.  All timing constructed are presented with statistics of occurences, and each of which can be examined in a waveform viewer by a simple mouse click.  This prevents design intents being overlooked, and potential issues getting into the final test patterns, which will be expensive to debug.
  • Cross-departmental Usability. With all complex tasks automated, TimeTable can be used by design verification, product engineering, and/or test engineering.  Whichever test development methodology you use, TimeTable is the right tool for the right job: redisocver design timing fast and accurately without manual intervention.

Cyclization is never easier with Solstice TimeTable.  Verification of the output can be done without re-simulation.

Vector Translation and Verification of VCD/EVCDs in Five Simple Steps

Step 1. Specify Target ATE and the Source VCD/EVCD to Convert From

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Step 2. Examine Auto-fill Pin List and Auto-Discover Timing

Solstice TimeTable imports a VCD/EVCD file and displays pin list found and timing automatically discovered from the file.


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Step 3. Adjust Global Group Timing or Specify Per-pin Timing

Global Group Timing is displayed on the top "DEFAULT" line to conveniently apply to all pins. Users only need to specify per-pin timing and Solstice TimeTable will produce exactly as spec'ed.

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Step 4. Launch Full Automation Scenario - VCD to Waveform to the target Test Program

Once timing is specified, Solstice TimeTable takes over with a full behind-the-scene automation to generate an ATE test program.

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Step 5. Instant Pattern Verification

Solstice TimeTable is the only software on the market to provide instant pattern verification without re-simulation. Discrepancies in the patterns before and after conversion are highlighted in red bars for visual inspection. Differences are searchable and can be reported in a list of exact locations.  

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Solstice TimeTable works with Excel Spreadsheet Format

Solstice TimeTable can be exported to Excel Spreadsheet format. Pin/Timing specified in Excel format can also be imported into Solstice TimeTable.

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