A True Virtual Test Methodology: Simulate ATE Patterns Directly on a Tester Model.  No Need to Translate Back to Testbench




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Version: 2018.0

Updated: November 2018


System Requirements: 

  • Linux 64-bit on Intel or AMD
  • Minimum: 6G RAM
  • Disk space: 50GB+
  • Redhat 4.8 or later
  • SuSE 11.x or later
  • Have access to one of the supported simulators listed below

Supported Simulators:

  • Cadence Xcelium
  • Mentor Questa
  • Synopsys VCS

Supported ATE's:

  • Advantest T2000 
  • Advantest V93000
  • Cohu LTXC DiamondX, X-series
  • Cohu LTXC Sapphire
  • Teradyne Catalyst
  • Teradyne J750
  • Teradyne UltraFLEX

Licensing Models:

  • Node Locked or Flexera FlexNET (FlexLM) Floating License
  • Time-based subscription or perpetual


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"TSSI VirtualTest allows the test engineer and the designer to speak the same language.  We took something that took 2 to 4 months and were able to do it in 24 hours.  We were able to find a circuit bug and the design team was able to fix it prior to silicon."

Mike Bourland - Principal Member of Technical Staff

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"With TVT, test engineers can now demonstrate in the design environment what they need rather than just trying to explain it."

Brent Baadsgaard - Test Engineering Manager


With TVT, you don't have to wait for the physical device to start validating your ATE test patterns, or verifying the device interaction with the tester.

TVT harnesses the simulation configuration of the device netlist and plugs in a Verilog model of the target tester.  In effect, TVT provides a virtual ATE environment for test engineers to bring up their ATE patterns early, while waiting for the physical device.  Design and test engineers can get a head start on their different verification needs in a common simulation environment at their workstation.

Cut Compilation and Program Debug Time in Half

Without re-translating ATE patterns back to a Verilog testbench, TVT compiles ATE program files directly and therefore, eliminates further distortion to the user ATE files.  Furthermore, TVT's intelligent compiler decouples stimulus/response data from the programming code that's being compiled.  The decoupling results in an extremely shorter compilation time because stimulus data don't need to be compiled and they are streamed in during simulation.  The decoupling also enables compile-once-simulate-many capability for design and test teams to perform rapid "spot checks" and 'what-if' analysis.

While modeling different capabilities from different ATE platforms, TVT provides a common user interface which lowers learning curves and increases productivity.

Essential Tool for Multi-Time Domain and Multi-Power Domain Debugs

TVT provides engineers with an easy-to-use virtual desktop ATE which can perform parallel simulations of multiple time domain patterns, or independent scan pattern bursts.

For low-power devices, it is essential to preserve the verification strategy specified in UPF (or CPF) when validating ATE patterns or the device will not be tested correctly especially with mulit-power domains.

Time Saving Features

  • Compile ATE program files directly without having to re-translate
  • Perform "Null DUT" (or shell/empty-socket) simulation for fast gross test (on syntax, connectivity, etc)
  • TVT's unique "Virtual Micro-Probes" enable full access beneath chip-level pins
  • Common user interface across different ATE platforms lowers learning curve and unifies methodologies
  • Support design's low-power verification which is usually the most challenging to debug with ATE patterns
  • Import/export of standard STDF error log format
  • OS Platform Independent: whether the target ATE platform is on Windows or Linux, TVT can facilitate compilation of test patterns in an enterprise Linux Load Sharing Facility (LSF)


Common Elusive Errors Detected by TVT

TVT delivers a proven method for uncovering design issues that could later compromise device characterization and approval.  In practical applications, users have seen design, configuration, test program and device issues highlighted through the use of TVT.

Test Bench Omissions

TVT simulates the translated vectors on the tester model, so test engineers can uncover errors that can be traced back to the designer's test bench or the translation process.  For example, the test bench may include vectors the designer needed during design but failed to remove when sending the vectors to test.  By running the vectors on TVT, test engineers can quickly isolate the problem in the test setup from those in the design vector set.  The design team can then compare the test simulation results with design simulation results and identify the differences, in some cases by just looking at the certain pins and making the corrections immediately.  Without TVT, it could take weeks to isolate these test-bench errors.

Timing Errors

Using TVT, test engineers can also identify errors caused by device initialization differences between the test bench and the pattern generated by the ATE.  TVT can help test teams discover if a device is attempting to run faster than the tester maximum and ultimately find an errors, such as an omitted clock divide stage.  A design change can then be made before first silicon, eliminating a wafer spin, and saving substantial costs and delays later in the project.

Read/Write Register Tests Fail on the Tester

Test teams can also isolate and debug simple logic errors (a reversed sequence of bit values) after duplicating the same failure on TVT and applying simulation debug techniques.

I/O Contention Errors

A common problem in tester setup typically occur when a device I/O pin is expected to be output but the tester's driver is still enabled.  In some cases, an I/O contention error can be caused by a tester characteristic that is not documented.  TVT can display waveforms which assist test engineers to locate problems and modify the vector set to prevent the contention from occurring. 

Non-Functional Patterns

This type of problem involves bad vectors and their simulation or translation errors.  By examining the TVT simulation output, test engineers can trace errors back to the first location where they occurred and compare the pattern with the pre-translated vector.  If they match correctly, the information can be communicated to the design team so they can trace the error location, and identify and resolve the problem.