Pre-Silicon Test Pattern Validation, Debug, and Re-target Solution  



  solstice screenshot

Version: 2017.1.2

Updated: December 21, 2017

Pricing and Licensing Terms: [Click Here >>]


What's New:

  • Instant pre- and post-translation waveform verification
  • Fast auto pin mapping between DUT ports and ATE pin names.
  • Step-by-Step testbench compile and simulation controls
  • Vector translation module: TimeTable
  • Standalone Low-cost Solstice for Chroma on Windows
  • Bug fixes in WaveMaker+, conditioners, and bridges (see more in Release Notes)

System Requirements:

  • Linux 64-bit (Intel or AMD)
  • Memory: 6GB
  • Disk space: 50GB
  • Operating system:
    • Redhat 4.8 or later;
    • SuSE 11.x or later;
    • CenTOS 6.x or later;
    • Must have openMotif 2.2.x installed.

Solstice-PV Users:

DFT Engineers

- Ensure pattern integrity after editing or merging

- Validate test patterns within design simulation environment

- Generate ATE-Ready patterns

Design Verification Engineers

- Validate scan, BIST, and JTAG patterns before silicon

Test Engineers

- Debug failing patterns

- Demonstrate failure conditions to design team

- Easy-to-use vector translation

Product Engineers

- Keep a predictable schedule

- Facilitate communication between design and test teams

- Correlate patterns across various format and platforms








Solstice-PV helps design and test teams to work in the same environment, using waveforms as the universal communication language.

Scan and functional patterns (ATPG, BIST, STIL, WGL, various ATE formats), including those from IP-core vendors, can be validated with the designer's DUT model for advanced preparation of test patterns, and more importantly, to perform early detection of problems that would cost millions of dollars if they slipped through tape-out into mask and silicon manufacturing processes.

Common Problems:

  • Test patterns keep coming back with issues
  • Pattern conversion and integration altered the designer's original intent
  • Design team depends on test team to get feedback on patterns quality
  • Long development cycles due to inaccurate communication between design and test
  • Lack of design and test automation and data correlation when debugging patterns (especially binary patterns)
  • Erroneous DUT behaviors when stimulated by cycle-based patterns
  • ATE-to-ATE migration errors
  • And more . . .

The Solstice "Change"

Solstice-PV changes the way design and test interact.

Design verification engineers can generate and validate their own test patterns or re-use a golden simulation flow in Solstice-PV's self-documented, executable flow-diagram to validate the converted patterns or ATE-specific patterns in the design simulation environment.

Test engineers can now get a head start in validating test pattern's functionality without the physical device. Instead of sending a problem report or screenshot of the waveform, test teams can communicate with the design team the precise failing location, the nature of the failure, and how the design team can reproduce the problem in the same simulation environment.

Key Features:

  • Reads ATE-Neutral test patterns (WGL, STIL, TDL, TSSI ASCII, JTAG, iJTAG*) and creates a simulation testbench
  • Reads ATE files (Advantest, LTXC, Teradyne) and creates a simulation testbench
  • Supports full pattern management tasks: merge, signal map, pin rename, etc
  • Supports customization and integration with customer internal tools via API
  • Comes with full featured waveform editor for instant viewing and editing of tester and DUT simulation outputs
  • Compares DUT response with test expected data and displays any errors on-the-fly and creates EDA diagnostic files for trace back to netlist
  • Supports instant viewing of failure log (STDF datalog) by simply drag and drop it directly onto waveform for failure analysis
  • Displays both design (event time stamps) and tester information (cycles, timesets, microcodes) in the same waveform environment
  • Works seamlessly with existing design environment supporting Cadence, Mentor, and Synopsys simulators
  • Retargets one ATE pattern format to another via a push-button process

*iJTAG pre-standard syntax.  Contact us if an up-to-date syntax support is needed


Easy-to-Use "Scenario Canvas" is Flow-based, Executable, and Self-Documented

Using Solstice-PV is as easy as point-and-click. For example, to validate a STIL pattern from ATPG, there are 3 simple steps:

  • Click to insert the Pattern Validation operation (pv)
  • Drag in the STIL file and let Solstice-PV auto-connect
  • Click Run!

That's it!  What's running under the hood is TSSI's 30+ years of award-winning innovations and technologies. TSSI's methodologies are sophisticated and automated so your validation process is as simple as possible in order to focus on more time sensitive tasks at-hand to produce quality devices.

  • First the built-in pattern conversion engine is automatically invoked to check the STIL file and at the same time, creating a random access database of stimulus and response, in preparation to stream into a Verilog logic simulator
  • Then a small testbench is created. It is small because the stimulus/response data have been de-coupled from Verilog code into a robust database complete with waveform editor for immediate data viewing and modification
  • Upon a successful preparation, Solstice-PV will prompt you to start a Verilog compilation and simulation run using your favorite logic simulator from Synopsys, Mentor Graphics, or Cadence
  • Simulation waveform along with any failures will be displayed on-the-fly as data are streamed in to the simulator. Design, test, and failure data are available in one environment for examination

[+] Click to enlarge image

Figure 1.  A STIL pattern from ATPG can be validated in a simple setup using Solstice-PV's Scenario canvas


The Solstice-PV Hover Interface

Viewing design and test data in one environment optimizes team communication and reveals the exact correlation of, for instance, a transition of an ATE pin in a tester cycle with a scan cell name, scan cycle and simulation timestamp. ATE time-set name can be mapped with an event sequence coded in a design testbench.


[+] Click to enlarge image

Figure 2.  Hover on the waveform to reveal both design and test information in one environment


Failure Analysis On-the-Fly

Solstice-PV's seamless integration with leading logic simulators enables immediate viewing of discrepancies between the expected state in the ATE patterns with that of the DUT.  Solstice-PV's robust graphical user interface (GUI) shows strobe placement and type (edge or window), the nature of failure, and the correlation of the design timestamp vs tester cycle.

Textual logs of failure information are also available for post-processing purposes in any of the custom simulation environment.

Drag and drop an error log file into Solstice-PV's waveform editor to get a visual of the failures.  Both EDA's error format (from simulators or ATPG tools) and STDF (ATE standard data failure format) are supported.

[+] Click to enlarge image

Figure 3.  The Hover Interface reveals additional context sensitive information at a failure location


Waveform Edit-in-Place

Simulation can be suspended with a mouse click in the Solstice-PV environment. The Edit-in-Place feature enables timing and pattern to be adjusted and then resume the simulation without Verilog re-compilation. This enables rapid troubleshooting by either the test or design verification team.

[+] Click to enlarge image

Figure 4.  Drag a drive edge and the underlined timing and pattern state will be updated


Click to Change Expected State

Changing an expected state from a '0' to a '1' is with a click of a button in the Solstice-PV environment. Masking is also done the same way when bypassing this failure condition is desired.

[+] Click to enlarge image

Figure 5. Changing an expected state with a right-mouse click


Expert in Making Educated Guess? Solstice-PV has a Feature for That!  The "Birdseye" View

There are times when experience reins supreme. Your prototype part failed in billions of cycles among thousands of pins and many are embedded in scan chains. Viewing a certain signature of failures could be just the hint you needed to hone in to a particular area of the design or a region of test patterns. Whether you're in design or test, Solstice-PV's snappy waveform zooming capability (enabled by the latest database random access techniques) gives you an overview of whether the failure is in a checker pattern, corners, symmetrical, or otherwise.

The "birdseye" view also displays any concentrations of failing regions.

[+] Click to enlarge image

Figure 6.  Look for failure signature is easy with the Birdseye View


Validate ATE-Specific Patterns!

Similar to validating STIL files, ATE-specific patterns are set up and processed the same way. In the screen shot below, a set of Advantest V93000 files are being validated. It's a set of pin, timing, and binary pattern files. Timing set number, equation set number, and spec set number are three additional parameters required by the V93000 file. These can be entered in Solstice-PV's PropertySheet, and the rest is the same as the STIL example above.

[+] Click to enlarge image

Figure 7.  Validating Advantest V93000 pattern file is also simple to do with Solstice-PV