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Frequently Asked Questions (FAQ)

General Questions

I needed a vector translation tool right now. How do I get it?

You can rent Solstice-TDS for as low as $600/month right on our website. We accept Visa and Master cards.

Once purchased online, you will receive a license file via email. The license will enable the software which you can download and install following very simple instructions.

For Windows-based testers, check out special low-cost packages:

What can Solstice-TDS do?

Solstice-TDS translates an EDA format (such as STIL, WGL, VCD, EVCD and many others) to a target tester format (such as Advantest V93000, Teradyne J750/UltraFLEX, LTX-Credence Diamondx and many others).

Solstice-TDS also generates a Verilog testbench from the converted ATE patterns for re-simulation in the design verification environment.

Go to the Solstice-TDS Product Page for more details.


What is Solstice-PV?

Solstice-PV is a pattern validation module within the Solstice-TDS software suite.

Solstice-PV reads ATE patterns and connects them with the designer's device netlist for re-simulation in the original verification testbench.

How is Solstice-PV different from other re-simulation methodologies?

Solstice-PV exercises the device netlist (DUT) via a robust and compact database of the tester patterns. Users can see simulation results as waveforms on-the-fly. What-if analysis of the ATE patterns can be done without re-compiling the testbench.

Go to the Solstice-PV Product Page for more details.

What's the difference between Solstice-PV's pattern validation and TSSI VirtualTest (TVT) pattern validation?

Solstice-PV converts test patterns (ATE-specific or ATE-neutral) to a test bench for re-simulation with the DUT model to validate the test patterns correctness.

TSSI VirtualTest (TVT), on the other hand, models the tester behavior by reading in the actual ATE files to validate ATE-specific syntax or programming errors. TVT also provides unique "virtual probes" for users to trace errors that are otherwise inaccessible when debugging patterns on a physical tester. TVT is the most accurate virtual test commercial product.

Go to the TSSI VirtualTest (TVT) tab below to see listing of key capabilities.

Both TSSI Solstice-PV and TVT support failure analysis by reading in error log files (STDF) for off-line pattern debug.

Solstice-PV is often used by design verification teams to validate their merged core patterns, functional and ATPG patterns. Solstice-PV can also perform vector translation to a specific ATE format for validation before delivery to their contract test-house.


How can I tell if my converted patterns are correct?

The easiest step is to compare your final waveforms (e.g., tester waveform) with your pre-converted waveforms (e.g., VCD).

Most commercial tools don't have a waveform display capability. With Solstice-TDS, it comes with a waveform display that can display VCD, EVCD, WGL, STIL, and tester waveforms.

Plus, Solstice-TDS compare waveforms of different formats and show differences.


What is the "wat" tool?
It stands for Waveform Analysis Tool. It is the fastest and most exhaustive timing and pattern extraction tool which cyclizes a VCD/EVCD file into ATE-friendly cycle-based patterns. Customers who are still using tpMatch, tpForceGen & tpStrobeGen should upgrade to this.
Why do I need to exhaustively analyze and preserve all transitions when I know the timing I want?
It is always best to know the timing. Then a "sampling" technique can be used to cyclize a VCD/EVCD file, which ignores unwanted transitions. However, when behaviors in a design simulation not communicated or documented, ignored transitions can result in incorrect or incomplete test patterns. It is worth the time to analyze and preserve all waveforms and be informed.
Why don't I hear much about the importance of waveform analysis in other tools?
Waveform Analysis Tool ("wat") is unique to TDS. When our customers are dealing with complex VCD/EVCD files, they have a choice to be comprehensive in seeing all waveforms/transitions handed over from design, or "sample" the files for fast results.
Can I choose between "sampling" and the "wat" technique in TDS?
Yes. TDS has a library of "conditioners" to assist customers in cyclizing VCD/EVCD files. From "sampling" well behaved simulation files to programmatically "condition" the VCD/EVCD files to remove glitches, align away drifting behaviors, or even synthesize internal control signals to accurately replicate design's control logic.
How to define a new signal (a control signal for instance)?

Use the Derive conditioner. This conditioner allows you to generate a completely new signal, following user definition. It can also be used to define a new signal based on Boolean equations using existing signals behavior.

Some examples below:

DAT1 IF ( CTL == ’H’ ) { D1 } DEFAULT { D2 }
Combination of two signals based on a third. DAT1 is created by using D1 when CTL is H and using D2 at all other times. (CTL, D1, and D2 are Source signals. 'H' is a TDS state character representing an "Expect High".)

CHG IF ( BEFORE 100ns ) { D2 } DEFAULT { D1 }
Combination based on absolute time. CHG is constructed to consist of D2 before 100ns and D1 after that time.

CLK2 { GENERATE ( ’D’ 20ns ’U’ 60ns ’D’ 20ns) }
Generation of a periodic signal from scratch. CLK2 starts with a 20nS D state followed by 60nS of U state, followed by a 20nS D state, then repeats this 100nS periodic signal.

Boolean expressions in TDS:

TDS Derive conditioner recognizes equality ("=="), AND, OR, NOT, and parentheses. For example:

IF ( ( AFTER 500ns ) AND NOT ( CLK == ’H’ ) )

In Boolean expressions, NOT has highest precedence (or binds most tightly), and AND takes precedence over OR. Parentheses may be used to force a different order of evaluation.

For more information, see TDS User Manual, or contact


Some wavebridges allow only I/O on the cycle edges, others also, or only support I/O in a cycle. what is the difference when putting together a timeplate?

Wavebridges that do not allow I/O-in-a-cycle (only I/O on the cycle borders), you will have only two tracks for the bidir signal: one for the output behavior , and one track to when it’s input. So, two tracks defined, one input and one output.

When the wavebridge also allow I/O during a cycle, three tracks might be created, depending on the need. You can end up having one Bidir track (I/O-in-a-cycle), one Input and one Output.

When doing cyclization, pay attention to the capabilities of the wavebridge to be used. You might have to consider possible restrictions.

Wavebridge issues errors complaining about things like "T0..T1>== 5ns". What does this mean?

A minimum width restriction for your target tester has been violated. In this case, the Wavebridge found one or more occasions when the minimum delay from timing edge T0 and timing edge T1 is less than 5ns.

Every tester has a list of force, compare, and drive constraints. All of them have to be met in order to conform to your target tester's rules, or your patterns will fail on the tester. The Wavebridge helps enforce these rules before you are testing the real part and having else time to re-generate patterns.

What's SEF, WDB, and SDB?

These are all TDS databases for storage efficiency, reduce redundant processes, and to provide application programming interface (API) for customer integration with their internal proprietary flow.

SEF stands for Standard Event Format. SEF contains print-on-change events reflecting design simulation events found in VCD, EVCD, and other legacy formats. All formats converted into SEF are normalized and therefore can be viewed and operated on by one set of database clients. This eliminates the risk of format-dependent variance.

WDB stands for WGL DataBase. This is a cyclized version of SEF where timing has been constructed using one of TDS tools, or simply from reading in a Waveform Generation Language (WGL) file or Standard Test Interface Language (STIL Std 1450.0) file where timings are pre-defined. Similar to the concept behind SEF, one of the big advantages in having a database is the ability to view/edit various data formats in waveforms.

SDB stands for STIL DataBase. This is the next-generation database to the WDB. All future TDS releases will support SEF's and SDB's. As the name stands, SDB supports STIL data structures natively. SDB is also a super set of, and is backward compatible to WDB.

How do I compare two SDBs? Or two SEFs? Or SDB with SEF?

Using the new WaveMakerPLUS Waveform Editor

Double-click to open the source database (SEF, WDB, or SDB). Drag the second one into the Waveform Editor view.
In the Waveform Editor you will now see two waveforms per pin, the top one corresponds to the source database initially opened (to be compared).

Using the Compare conditioner

The Compare Conditioner module accepts two waveform database files, compares the two, and produces a report of the differences and, optionally, a new SEF database. This new database contains signal sets from each pair of original signals (renamed to encode the sources) and a difference signal that describes the time regions where the original signals differ.

How can I remove signals from an SEF without GUI?
Just add a Derive conditioner to your flow. This conditioner reads the source SEF and the Signal Derivation File (derive file). Each line in derive file names the signals you want to keep in the destination SEF. However, to apply this functionality the Derive conditioner must have its operation mode set to REPLACE. Only signals named in derive file are included in the destination database. This is different from many Conditioners, which copy all signals not specified for modification directly from source to destination. The order of the signals in the destination is the same as the order in the derive file.
I'm getting too many timeplates with TpForcegen. What can I do?

The short answer is to upgrade to the Waveform Analysis Tool (the "WAT").

Alternatively, you will have to edit the shape file being used by TpForceGen, for the specified tester.
Check how you can change the available shapes for the timeplates in order to reduce the number of time plates created.
By doing this, you are "forcing" TpForcegen to make better use of shapes like S and P, and shape combinations involving them.
You can find TDS shape files in your TDS tree (shape files have extension .shp):


Heard about the Signal Edit Conditioner for WDBs. What can it do?

This conditioner reads an input WDB and user-defined edit operations, specified either on the property sheet or in an optional operation file or "opfile", and generates an output WDB with edits applied.

Applications where the conditioner could be useful include:

- manipulation of WDBs generated by ATPG tools
- manipulation of WDBs provided by IP core vendors
- manipulation of WDBs coming from external WGL sources.

Five classes of WDB edit operations are currently supported:

- add
- delete
- rename
- promote2bidir
- matchpinfile

Signal_edit users requiring only a single edit operation affecting a single signal can run without an operation file, specifying a single edit operation and target signal on the property sheet. If multiple signals are to be edited, a textual opfile may be defined specifying a set of signals to be edited. The majority of applications would specify a single class of edits (add | delete | rename | promote2bidir) which is applied to one or more signals depending on if an opfile is used.

The edit operations supported by the conditioner primarily involve manipulation of the "signal" dimension of WDB, though selected operations access and edit the WDB timeplates as required. There is no support for adding pattern data in WDB patterns in the current version, though the delete, rename, and promote2bidir operations make appropriate adjustments to the WDB pattern space for their respective operations.

A number of the operations supported by the conditioner are alternatively supported thru the WaveMaker GUI interface, though the process could become involved depending on the class of edit operation, and is a manual process requiring user-specification
Other operations have no direct WaveMaker counterpart and currently require that the user perform the operation in multiple upstream TDS processes or thru text editing of WGL.

TSSI VirtualTest (TVT)

What's the difference between TVT and DVT?

TVT is the next-generation virtual test by TSSI based on the award winning Digital Virtual Test product line. TSSI drops the "Digital" in the name because TVT is designed to be ready for mixed-signal analog validation.

What are TVT's unique capabilities?

In addition to emulating ATE patterns, TVT can model:

  • Match Loops
  • Multi-Ports
  • Multiple Time Domain
  • DC-level setup
  • Pattern microcodes such as V93K's GENV, RPTV, etc.
  • ATE specific memory word size such as V93K's modulo-8 vs modulo-7 modes
  • Broadside loading scan patterns is a great performance enhancer. Various scan patterns can be isolated or bypassed when all scanout flops are pre-loaded for capture
  • Designed for Analog Mixed-Signal modeling
  • Designed to be run by the ATE's user interface

TD-ScanPro for National Instruments (NI)

What does TD-ScanPro for NI support?

TD-ScanPro reads WGL and STIL scan patterns and generates NI's new STS format (digitpat, digitiming, etc) ready to load onto the PXIe 6570 card

TD-ScanPro is the next-generation of TD-Scan and TD-Sim, so it also supports all the cards TD-SCAN supports by generating the old waveform-based syntax (".hws").

Moreover, TD-ScanPro reads more than just WGL and STIL patterns. It can also convert VCD and EVCD.

TD-SCAN users are recommended to upgrade to this new version at a discount price.

Go to the TD-ScanPro Product Page for more details.

TD-SCAN for National Instruments (NI) - A Subset of TD-ScanPro

What does TD-Scan for NI support?

TD-SCAN for NI reads WGL and STIL scan patterns and generates a file to be imported into NI's LabVIEW environment.

The NI instruments TD-SCAN for NI currently supports are:

  • PXI/PCI-6541/6542
  • PXI/PCI-6544/6545
  • PXI/PCI-6547/6548
  • PXI/PCI-6551/6552
  • PXI/PCI-6561/6562

If you needed support for an instrument that's not listed above, or if you needed to convert VCD or other formats to an NI instrument, please contact your local National Instruments contact or email us at Additional information is available [Click Here]

I have a huge ATPG file that seems to slow TD-SCAN down to almost a halt. What do I do?
Invoke TD-SCAN with the "-bigscan" option. This will specify that file-based (as opposed to in-memory) scan data to be used.  Make this the first option in the TD-SCAN command line.
Does TD-Scan LabVIEW API support edge positioning bidirectionally?
Yes. You can make it work by modifying the input XML file to the TSSI API. See details at this NI KnowledgeBase area: