Correcting Mistimed I/O


Output vectors from logic simulators usually require some level of modification before they’re ready for tester programs to use. The EDA world is the unconstrained world of software, where the only limitations are those imposed by the software itself. Device simulations can be run at virtually any rate and resolution. ATEs, however, live in the physical world, where there are real hardware and resource limitations. In order for simulation waveforms to be useable in a functional test program, they must be “groomed” to take tester requirements and device specifications into account.

Let’s look at how I/O timing errors can be introduced in simulation runs, and what we can do to correct them. The problem originates in the way I/O information is handled in the two environments.

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