Digital Virtual Tester (DVT) Now you don’t have to wait for the physical device to start testing. DVT harnesses the power of electronic design simulation using powerful software models of the target tester. Design and test engineers can verify the test database with the design model in the simulation environment at their workstation.
Cut Test Debug Time in Half DVT eliminates up to 80 percent of the time typically devoted to test debug. Using DVT, design and test engineers can:
Compile, load, and check the test program
Perform a “null DUT” empty-socket test on demand for fast program syntax verification
Connect device and ATE models and run full tests
View logs and waveforms
Use DVT's unique "Virtual-Microprobe” to pinpoint defects in design and test program debugs within the Verilog simulation environment
Essential Tool for Multi-Domain Debug DVT provides engineers with an easy-to-use Virtual Desktop ATE which enables virtual testing and increases productivity, saving precious time and money. DVT allows design and test engineers to:
Perform device-to-tester interaction
Debug and verify timing and test patterns without re-translating them back to Verilog Testbench
Confirms accuracy of test systems when silicon arrives
Supported Simulators:
Cadence NC-Sim, NC-Verilog, Verilog-XL
Mentor Graphics ModelSim
Synopsys VCS
Supported Automatic Test Equipment (ATE):
Advantest T33xx, T66xx, T65xx
Credence Quartet/Duo/Vista, Kalos, NPTest Schlumberger ITS9000, IMS Vanguard/ATS, SZ Systems
